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DS1921G
Thermochron iButton Device
A t RSTL duration of 480μs or longer exits the overdrive
mode, returning the device to standard speed. If the
DS1921G is in overdrive mode and t RSTL is no longer
than 80μs, the device remains in overdrive mode.
After the bus master has released the line, it goes into
receive mode (Rx). Now the 1-Wire bus is pulled to
V PUP through the pullup resistor or, in case of a
DS2480B driver, through active circuitry. When the
threshold V TH is crossed, the DS1921G waits for t PDH
and then transmits a presence pulse by pulling the line
low for t PDL . To detect a presence pulse, the master
must test the logical state of the 1-Wire line at t MSP .
The t RSTH window must be at least the sum of t PDHMAX ,
t PDLMAX , and t RECMIN . Immediately after t RSTH is
expired, the DS1921G is ready for data communication.
In a mixed population network, t RSTH should be extend-
ed to minimum 480μs at standard speed and 48μs at
overdrive speed to accommodate other 1-Wire devices.
Read/Write Time Slots
Data communication with the DS1921G takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. The definitions of the
write and read time slots are illustrated in Figure 15.
All communication begins with the master pulling the
data line low. As the voltage on the 1-Wire line falls
below the threshold V TL , the DS1921G starts its internal
timing generator that determines when the data line is
sampled during a write time slot and how long data is
valid during a read time slot.
Master-to-Slave
For a write-one time slot, the voltage on the data line
must have crossed the V TH threshold after the write-one
low time t W1LMAX is expired. For a write-zero time slot,
the voltage on the data line must stay below the V TH
threshold until the write-zero low time t W0LMIN is expired.
The voltage on the data line should not exceed V ILMAX
during the entire t W0L or t W1L window. After the V TH
threshold has been crossed, the DS1921G needs a
recovery time t REC before it is ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below V TL
until the read low time t RL is expired. During the t RL
window, when responding with a 0, the DS1921G starts
pulling the data line low; its internal timing generator
determines when this pulldown ends and the voltage
starts rising again. When responding with a 1, the
DS1921G does not hold the data line low at all, and the
voltage starts rising as soon as t RL is over.
32
The sum of t RL + δ (rise time) on one side and the inter-
nal timing generator of the DS1921G on the other side
define the master sampling window (t MSRMIN to
t MSRMAX ) in which the master must perform a read from
the data line. For most reliable communication, t RL
should be as short as permissible and the master
should read close to but no later than t MSRMAX . After
reading from the data line, the master must wait until
t SLOT is expired. This guarantees sufficient recovery
time t REC for the DS1921G to get ready for the next
time slot.
CRC Generation
There are two different types of CRCs with the
DS1921G. One CRC is an 8-bit type and is stored in the
most significant byte of the 64-bit ROM. The bus master
can compute a CRC value from the first 56 bits of the
64-bit ROM and compare it to the value stored within
the DS1921G to determine if the ROM data has been
received error-free. The equivalent polynomial function
of this CRC is X 8 + X 5 + X 4 + 1. This 8-bit CRC is
received in the true (noninverted) form. It is computed
at the factory and lasered into the ROM.
The other CRC is a 16-bit type, generated according to
the standardized CRC-16 polynomial function X 16 +
X 15 + X 2 + 1. This CRC is used for error detection when
reading data memory using the Read Memory with
CRC command and for fast verification of a data trans-
fer when writing to or reading from the scratchpad. In
contrast to the 8-bit CRC, the 16-bit CRC is always
communicated in the inverted form. A CRC-generator
inside the DS1921G chip (Figure 16) calculates a new
16-bit CRC as shown in the command flowchart of
Figure 10. The bus master compares the CRC value
read from the device to the one it calculates from the
data and decides whether to continue with an operation
or to reread the portion of the data with the CRC error.
With the initial pass through the Read Memory with
CRC flowchart, the 16-bit CRC value is the result of
shifting the command byte into the cleared CRC gener-
ator, followed by the 2 address bytes and the data
bytes. Subsequent passes through the Read Memory
with CRC flowchart generate a 16-bit CRC that is the
result of clearing the CRC generator and then shifting in
the data bytes.
With the Write Scratchpad command, the CRC is gener-
ated by first clearing the CRC generator and then shift-
ing in the command code, the target addresses TA1
and TA2, and all the data bytes. The DS1921G transmits
this CRC only if the data bytes written to the scratchpad
include scratchpad ending offset 11111b. The data can
start at any location within the scratchpad.
Maxim Integrated
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